65 6502 SBC FPGA
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Overview / Component 02
Graphics

VIC graphics $8000 · $9000

The video controller produces the picture: text, color and several bitmap modes — output as VGA or HDMI, timed straight from FPGA logic.

What it is

The VIC (Video Interface Controller) is the system's graphics block. It reads character, color and bitmap data from video RAM and turns it into a complete video signal with its own horizontal and vertical sync — HDMI/DVI on the Tang Primer 20K, VGA on the PIX16.

Resolution
640×480 @ 60 Hz
Pixel clock
27 MHz
Text mode
40×25, 16 colors
Bitmap modes
1-bpp · RGB332 · RGB222

What it does

Text mode

40×25 characters, each 2× scaled (16×16 screen pixels). Character patterns live in the char_rom (8×8 pixels, bit 7 = reverse video). Each cell has its own foreground and background color from color RAM at $8400, packed as bg[7:4] | fg[3:0]. The 16-color palette is a Pepto-style C64 RGB565 lookup.

Bitmap modes

The 16 KB framebuffer is exposed through an 8 KB CPU window at $6000–$7FFF; a MODE bit selects the bank. The control register $9000 switches between modes.

Bus stealing — the shared bus

VIC and CPU share a single-port video memory. During each horizontal blanking interval the VIC prefetches the next display line and holds the CPU via the RDY pin. The overhead is small: ~4.8 % in text mode, with a worst case of 9.4 % for RGB332. CPU writes to video RAM are never lost — a pending write is buffered and committed on the first free clock.

Color registers

AddressRegisterFunction
$9000MODEbit 0 bitmap, bit 1 RGB332, bit 2 bank, bit 3 RGB222
$9003TEXT_COLORforeground color 0–15
$9004BG_COLORbackground color 0–15

From BASIC

REM bitmap mode on, set a pixel
POKE 36864, 1
A=24576+Y*40+INT(X/8)
POKE A, PEEK(A) OR 2^(7-(X AND 7))
POKE 36864, 0          : REM back to text