T65 CPU core Reset @ $FFFC

What it is

The T65 is an open-source, cycle-accurate VHDL recreation of the MOS 6502 processor. Instead of soldering a real 6502 IC, the soft core describes the CPU's behavior in logic, which the FPGA toolchain synthesizes into the device fabric. The same machine the C emulator models now runs directly in hardware.

Between core and system sits a project-specific bus adapter (t65_adapter.vhd) that maps the T65's 24-bit address bus down to the SBC's 16-bit address space and cleanly couples the write strobe, write data and read data input (DI) to memory and peripherals.

What it does

The core fetches instructions, decodes them and executes the full 6502 instruction set — including all addressing modes, stack operations and interrupt handling.

• Half system clock: A cpu_enable signal toggles on every 54 MHz system clock, so the T65 advances at effectively up to 27 MHz. Writes are committed on the cpu_enable = '0' half-cycle — matching synchronous FPGA writes and asynchronous reads.
• Reset sequence: After reset_n is released, the CPU runs its 7 internal cycles and reads the reset vector from $FFFC–$FFFD in ROM before jumping to the start address.
• Interrupts: The IRQ sources from VIA, UART and VIC are OR-combined (cpu_irq_n = NOT (via_irq OR uart_irq OR vic_irq)); the core branches through the vector at $FFFE–$FFFF.
• Bus stealing: Through the RDY input the VIC holds the CPU while it uses the blanking interval to fetch video data — without the CPU losing any writes.

Clocking

A single 27 MHz oscillator feeds a 270 MHz PLL. From it come the 54 MHz system clock (270 / 5), the 135 MHz TMDS clock and the 27 MHz pixel clock. The CPU core runs at half the system clock via the toggle scheme — fast enough to run BASIC and machine code smoothly.

Where it lives in the code

File	Role
third_party/t65/rtl/	Imported T65 core (CPU, ALU, microcode)
rtl/core/cpu/t65_adapter.vhd	16-bit bus adapter, write/read glue
rtl/core/sbc_t65_top.vhd	Fully integrated system top with T65

Verified by GHDL testbenches: boot from a real 6502 ROM (LDA #$42; STA $0002), UART output, VIA port driving, Timer-1 IRQ handling and a kernel smoke test with composed kernel.rom + msbasic.rom.